ABOUT VLSI PROJECT
VLSI full form Very-large-scale integration (VLSI) design is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began when complex semiconductor and communication technologies were being developed. VLSI 2020 2021 IEEE projects in Chennai is a technology by which 10000-1 Million transistors can be fabricated on a single chip. In today’s world VLSI technology is widely used in various branches of Engineering like Voice and Data Communication networks, Digital Signal Processing, Computers, Commercial Electronics, Automobiles, Medicine, and many more.
Here at FPGA projects are implemented in vlsi programming either in Verilog or VHDL coding using Xilinx software and the bit code is generated from this which can be dumped on FPGA kits. Mtech vlsi projects would include the kit implementation which can be done on spartan 3a, spartan 3e, and spartan 6 based on the IEEE VLSI paper chosen. We also offer ieee vlsi based projects for ECE final year students and Mtech ECE students.
B.Tech final year projects students can also reach us if they are willing for industrial tool specifications such as cadence orcad, Xilinx FPGA implementation(VHDL Verilog HDL), Tanner EDA, AVR studio, MATLAB, H-spice, P-spice, Modalism, Network simulator2, Proteaus, and many more to follow. Major projects and mini projects in VLSI for ECE students.
IEEE VLSI DOMAIN LIST 2020-2021
| SNO | Projects List |
|---|---|
| 1 | A Modified Partial Product Generator for Redundant Binary Multipliers |
| 2 | An Efficient Hardware Implementation of Canny Edge Detection Algorithm |
| 3 | Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation |
| 4 | A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications |
| 5 | The Serial Commutator (SC) FFT |
| 7 | An Improved Signed Digit Representation Approach for Constant Vector Multiplication |
| 8 | High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels |
| 9 | A New XOR-Free Approach for Implementation of Convolutional Encoder |
| 10 | Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology |
| 11 | Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation |
| 12 | Implementation of a PID control PWM Module on FPGA |
| 13 | Built-in Self Testing of FPGAs |
| 14 | An FPGA-Based Cloud System for Massive ECG Data Analysis |
| 15 | Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip |
| 16 | VLSI Implementation of Fully Parallel LTE Turbo Decoders |
